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| NTMS10P02R2 Product Preview HDTMOS3e Single SO-8 P-Channel Enhancement-Mode Power MOSFET Features * * * * * * * Ultra Low RDS(on) Higher Efficiency Extending Battery Life Logic Level Gate Drive Miniature SO-8 Surface Mount Package Diode Exhibits High Speed, Soft Recovery Avalanche Energy Specified SO-8 Mounting Information Provided http://onsemi.com P-Channel D G S Applications * Power Management in Portable and Battery-Powered Products, i.e.: Cellular and Cordless Telephones and PCMCIA Cards MAXIMUM RATINGS (TJ = 25C unless otherwise noted) Rating Drain-to-Source Voltage Gate-to-Source Voltage -- Continuous Thermal Resistance -- Junction-to-Ambient (1.) Total Power Dissipation @ TA = 25C (1.) Continuous Drain Current @ 25C (1.) Continuous Drain Current @ 70C (1.) Maximum Operating Power Dissipation (2.) Maximum Operating Drain Current (2.) Pulsed Drain Current (5.) Thermal Resistance -- Junction-to-Ambient (4.) Total Power Dissipation @ TA = 25C (3.) Continuous Drain Current @ 25C (3.) Continuous Drain Current @ 70C (3.) Maximum Operating Power Dissipation (4.) Maximum Operating Drain Current (4.) Pulsed Drain Current (5.) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy -- Starting TJ = 25C (VDD = -20 Vdc, VGS = -4.5 Vdc, Peak IL = 5.0 Apk, L = 40 mH, RG = 25 ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VGS RJA PD ID ID PD ID IDM RJA PD ID ID PD ID IDM TJ, Tstg EAS Value -20 "12 50 2.5 -10 -8.0 0.6 -5.5 -50 80 1.6 -8.8 -6.4 0.4 -4.5 -44 -55 to +150 500 Unit Vdc Vdc C/W W A A W A A C/W W A A W A A C mJ 8 1 SO-8 CASE 751 STYLE 12 MARKING DIAGRAM E10P02 LYWW E10P02= Device Code L = Assembly Location Y = Year WW = Work Week PIN ASSIGNMENT Source Source 2 3 4 1 8 7 6 5 Drain Drain Drain Drain TL 260 C Source Gate 1. Mounted onto a 2 square FR-4 Board (1 sq. Cu 0.06 thick single sided), t = 10 seconds. 2. Mounted onto a 2 square FR-4 Board (1 sq. Cu 0.06 thick single sided), t = steady state. 3. Minimum FR-4 or G-10 PCB, t = 10 seconds. 4. Minimum FR-4 or G-10 PCB, t = steady state. 5. Pulse Test: Pulse Width < 300 ms, Duty Cycle < 2%. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Top View ORDERING INFORMATION Device NTMS10P02R2 Package SO-8 Shipping 2500/Tape & Reel (c) Semiconductor Components Industries, LLC, 2000 1 August, 2000 - Rev. 1 Publication Order Number: NTMS10P02R2/D NTMS10P02R2 ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted) * Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = -250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 25C) (VDS = -20 Vdc, VGS = 0 Vdc, TJ = 70C) Gate-Body Leakage Current (VGS = -12 Vdc, VDS = 0 Vdc) Gate-Body Leakage Current (VGS = +12 Vdc, VDS = 0 Vdc) ON CHARACTERISTICS Gate Threshold Voltage (VDS = VGS, ID = -250 Adc) Temperature Coefficient (Negative) Static Drain-to-Source On-State Resistance (VGS = -4.5 Vdc, ID = -10 Adc) (VGS = -2.5 Vdc, ID = -8.8 Adc) Forward Transconductance (VDS = -10 Vdc, ID = -10 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge BODY-DRAIN DIODE RATINGS Diode Forward On-Voltage Diode Forward On-Voltage Reverse Recovery Time (IS = -2.1 Adc, VGS = 0 Vdc, 2 1 Ad Vd dIS/dt = 100 A/s) Reverse Recovery Stored Charge 6. Indicates Pulse Test: Pulse Width = 300 s max, Duty Cycle = 2%. 7. Switching characteristics are independent of operating junction temperature. * Handling precautions to protect against electrostatic discharge is mandatory. (6.) (6.)(7.) Symbol Min Typ Max Unit V(BR)DSS -20 -- IDSS -- -- IGSS -- IGSS -- -- 100 -- -100 -- -- -1.0 -5.0 -- -12.1 -- -- Vdc mV/C Adc nAdc nAdc VGS(th) -0.6 -- RDS(on) -- -- gFS -- 0.012 0.017 30 0.014 0.020 -- -0.88 2.8 -1.20 -- Vdc mV/C Mhos Ciss (VDS = -16 Vdc, VGS = 0 Vdc, 16 Vd Vd f = 1.0 MHz) Coss Crss -- -- -- 3100 1100 475 3640 1670 1010 pF td(on) (VDD = -10 Vdc, ID = -1.0 Adc, VGS = -4.5 Vdc, -4 5 Vdc RG = 6.0 ) tr td(off) tf td(on) (VDD = -10 Vdc, ID = -10 Adc, VGS = -4.5 Vdc, -4 5 Vdc RG = 6.0 ) tr td(off) tf (VDS = -10 Vdc, VGS = -4.5 Vdc, ID = -10 Adc) 10 Ad ) Qtot Qgs Qgd -- -- -- -- -- -- -- -- -- -- -- 25 40 110 110 25 100 100 125 48 6.5 17 35 65 190 190 -- -- -- -- 70 -- -- ns ns nC (IS = -2.1 Adc, VGS = 0 Vdc) (IS = -2.1 Adc, VGS = 0 Vdc, TJ = 125C) (IS = -10 Adc, VGS = 0 Vdc) (IS = -10 Adc, VGS = 0 Vdc, TJ = 125C) VSD VSD trr ta tb QRR -- -- -- -- -- -- -- -- -0.72 -0.60 -0.90 -0.75 65 25 40 0.075 -1.2 -- -- -- 100 -- -- -- Vdc Vdc ns C http://onsemi.com 2 NTMS10P02R2 20 -2.3 V -2.1 V -I D , DRAIN CURRENT (AMPS) 10 VDS -10 V TJ = 25C -1.9 V 8.0 -I D , DRAIN CURRENT (AMPS) 15 -10 V -3.1 V 6.0 25C 10 4.0 5.0 VGS = -1.7 V 2.0 0 100C TJ = -55C 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2.00 0 0.5 1.0 1.5 2.0 2.5 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) Figure 1. On-Region Characteristics R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) R DS(on), DRAIN-TO-SOURCE RESISTANCE (OHMS) Figure 2. Transfer Characteristics 0.100 ID = -10 A TJ = 25C 0.075 0.020 TJ = 25C VGS = -2.5 V 0.016 0.050 VGS = -4.5 V 0.012 0.025 0 0 2.0 4.0 6.0 8.0 -VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 10 0.008 6.0 10 14 -ID, DRAIN CURRENT (AMPS) 18 R DS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) Figure 3. On-Resistance versus Gate-To-Source Voltage 1.6 ID = -10 A VGS = -4.5 V -I DSS , LEAKAGE (nA) 1000 10,000 Figure 4. On-Resistance versus Drain Current and Gate Voltage VGS = 0 V 1.4 TJ = 125C 1.2 1.0 TJ = 100C 100 0.8 0.6 -50 10 -25 0 25 50 75 100 125 TJ, JUNCTION TEMPERATURE (C) 150 2.0 6.0 10 14 18 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 5. On-Resistance Variation with Temperature Figure 6. Drain-To-Source Leakage Current versus Voltage http://onsemi.com 3 NTMS10P02R2 10,000 VGS = 0 V C, CAPACITANCE (pF) 8000 Ciss VDS = 0 V TJ = 25C 6000 Crss 4000 Ciss 2000 Crss 0 10 5.0 0 5.0 -VGS -VDS 10 Coss 15 20 GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation -VGS , GATE-TO-SOURCE VOLTAGE (VOLTS) -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 5.0 QT 4.0 VGS 8.0 10 VDS 3.0 Q1 2.0 ID = -10 A TJ = 25C Q2 6.0 4.0 1.0 0 0 Q3 2.0 0 10 20 30 40 50 Qg, TOTAL GATE CHARGE (nC) Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge 1000 VDD = -10 V ID = -1.0 A VGS = -4.5 V t, TIME (ns) td(off) tf t, TIME (ns) 1000 VDD = -10 V ID = -10 A VGS = -4.5 V td(off) tr tf 100 td(on) tr 100 td(on) 10 1.0 10 RG, GATE RESISTANCE (OHMS) 100 10 1.0 10 RG, GATE RESISTANCE (OHMS) 100 Figure 9. Resistive Switching Time Variation versus Gate Resistance Figure 10. Resistive Switching Time Variation versus Gate Resistance http://onsemi.com 4 NTMS10P02R2 DRAIN-TO-SOURCE DIODE CHARACTERISTICS 100 -IS, SOURCE CURRENT (AMPS) -ID , DRAIN CURRENT (AMPS) 2.0 1.6 1.2 0.8 0.4 0 VGS = 0 V TJ = 25C 100 ms 10 1.0 ms 1.0 VGS = 2.5 V SINGLE PULSE TC = 25C RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1.0 10 10 ms 0.1 0.50 0.55 0.60 0.65 0.70 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) dc 100 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current Figure 12. Maximum Rated Forward Biased Safe Operating Area di/dt IS trr ta tb TIME tp IS 0.25 IS Figure 13. Diode Reverse Recovery Waveform TYPICAL ELECTRICAL CHARACTERISTICS 10 Rthja(t)EFFECTIVE TRANSIENT , THERMAL RESISTANCE 1.0 D = 0.5 0.2 0.1 0.05 0.02 0.01 Chip 0.0163 0.1 Normalized to ja at 10s. 0.0652 0.1988 0.6411 0.9502 0.01 0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 t, TIME (s) 1.0E+00 1.0E+01 1.0E+02 Ambient 1.0E+03 Figure 14. Thermal Response http://onsemi.com 5 NTMS10P02R2 INFORMATION FOR USING THE SO-8 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self-align when subjected to a solder reflow process. 0.060 1.52 0.275 7.0 0.155 4.0 0.024 0.6 0.050 1.270 inches mm SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. * Always preheat the device. * The delta temperature between the preheat and soldering should be 100C or less.* * When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10C. * The soldering temperature and time shall not exceed 260C for more than 10 seconds. * When shifting from preheating to soldering, the maximum temperature gradient shall be 5C or less. * After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. * Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 6 NTMS10P02R2 TYPICAL SOLDER HEATING PROFILE For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 15 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. STEP 1 PREHEAT ZONE 1 RAMP" 200C STEP 2 STEP 3 VENT HEATING SOAK" ZONES 2 & 5 RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150C STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 SPIKE" SOAK" 170C 160C STEP 6 VENT STEP 7 COOLING 205 TO 219C PEAK AT SOLDER JOINT 150C 100C 100C 140C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) 50C DESIRED CURVE FOR LOW MASS ASSEMBLIES TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 15. Typical Solder Heating Profile http://onsemi.com 7 NTMS10P02R2 PACKAGE DIMENSIONS SO-8 CASE 751-06 PLASTIC ISSUE T A 8 D 5 C E H 1 4 0.25 M B M h B C e A SEATING PLANE X 45 _ NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ SOURCE SOURCE SOURCE GATE DRAIN DRAIN DRAIN DRAIN q 0.10 A1 B 0.25 M L CB S A S STYLE 12: PIN 1. 2. 3. 4. 5. 6. 7. 8. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION NORTH AMERICA Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com Fax Response Line: 303-675-2167 or 800-344-3810 Toll Free USA/Canada N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (Mon-Fri 2:30pm to 7:00pm CET) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (Mon-Fri 2:00pm to 7:00pm CET) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (Mon-Fri 12:00pm to 5:00pm GMT) Email: ONlit@hibbertco.com EUROPEAN TOLL-FREE ACCESS*: 00-800-4422-3781 *Available from Germany, France, Italy, UK, Ireland CENTRAL/SOUTH AMERICA: Spanish Phone: 303-308-7143 (Mon-Fri 8:00am to 5:00pm MST) Email: ONlit-spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong & Singapore: 001-800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 NTMS10P02R2/D |
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